1. Technical Field
The invention disclosed broadly relates to data processing systems and more particularly relates to a system and method for high availability data processing, using finite state machines.
2. Related Patent Applications
This patent application is related to the copending U.S. patent application Ser. No. 08/024,572, filed Mar. 1, 1993, entitled "Information Collection Architecture and Method for a Data Communications Network," by J. G. Waclawsky, Paul C. Hershey, Kenneth J. Barker and Charles S. Lingafelt, Sr., assigned to the IBM Corporation and incorporated herein by reference. Now U.S. Pat. No. 5,375,070.
This patent application is also related to the copending U.S. patent application, Ser. No. 08/024,563, filed Mar. 1, 1993, entitled "Event Driven Interface for a System for Monitoring and Controlling a Data Communications Network," by Paul C. Hershey, John G. Waclawsky, Kenneth J. Barker and Charles S. Lingafelt, Sr., assigned to the IBM Corporation and incorporated herein by reference. Now U.S. Pat. No. 5,365,514.
This patent application is also related to the copending U.S. patent application, Ser. No. 08/024,542, filed Mar. 1, 1993, entitled "System and Method for Configuring an Event Driven Interface and Analyzing Its output for Monitoring and Controlling a Data Communications Network," by John G. Waclawsky and Paul C. Hershey, assigned to the IBM Corporation and incorporated herein by reference. Now U.S. Pat. No. 5,493,689.
This patent application is also related to the copending U.S. patent application, Ser. No. 08/138,045, filed Oct. 15, 1993, entitled "System and Method for Adaptive, Active Monitoring of a Serial Data Stream having a Characteristic Pattern," by Paul C. Hershey and John G. Waclawsky, assigned to the IBM Corporation and incorporated herein by reference.
3. Background Art
Finite state machines (FSM) are commonly used in the implementation of telecommunications protocols and of input/output processors, because finite state machines can define all possible conditions completely and unambiguously. However, a problem with finite state machines is defining the sequence of states and the accompanying actions to be accomplished with each state. Conventional implementations of finite state machines result in program code sets which are extensive and complex. This problem has been solved by the "System and Method for Adaptive, Active Monitoring of a Serial Data Stream having a Characteristic Pattern," by Paul C. Hershey, et al., cited above. The adaptive, active monitor comprises finite state machines (FSM) which are constructed to detect the occurrence of a characteristic data pattern in a bit stream. If the FSM successfully detects the pattern, it then outputs a pattern alarm signal, indicating the successful detection of the characteristic data pattern.
One feature of the adaptive, active monitor invention is the programmability of the finite state machines (FSMs) and the programmability of their interconnection. Each FSM consists of an address register and a memory. The address register has two portions, an n-X bit wide first portion and a X-bit wide second portion. X is one bit for binary data, X is a word of two bits for Manchester encoded data, or X is a word of five bits for FDDI encoded data. The X-bit wide portion is connected to the input data stream which contains the characteristic data pattern of interest. The n-X bit wide portion contains data which is output from the memory. The next address to be applied by the address register to the memory is made up of the n-X bit wide portion and the next arriving X-bit word from the input data stream.
Each memory has a plurality of data storage locations, each having a first portion with n-X bits, to be output to the address register as part of the next address. Many of the memory locations have a second portion which stores a command to reset the address register if the FSM fails to detect its designated component bit pattern.
A terminal location in the memory of an FSM will include a start signal value to signal another FSM to start analyzing the data stream. If the terminal location in a predecessor FSM memory is successful in matching the last bit of its designated component bit pattern, then it will output a starting signal to a succeeding FSM. The succeeding FSM will begin analyzing the data stream for the next component bit pattern of the characteristic data pattern. The memory of an FSM can be a writable RAM, enabling its reconfiguration to detect different component bit patterns.
A long standing problem in data processing technology is the provision of highly reliable systems for continuous availability of the data processing resource. Redundant systems have been configured in the prior art, to provide a standby processor to take the place of a primary processor when the primary fails. Various techniques have been used to initiate the switchover of the standby processor. The standby may be running the same program as the primary, in synchronism with the primary, but the standby generates no output. The standby monitors a heartbeat signal from the primary, to periodically check the health of the primary. If the standby senses that the primary is failing, the standby will switchover to perform the functions of the primary, generating the output that had been generated by the primary. The control of the switchover can be initiated by the standby signalling the primary to stop, while the standby takes over the primary's functions. This is known as a hot-standby configuration.
The problem with this prior art approach to high availability, is that the control of the monitoring of the heartbeat and the switchover is done by a sequence of programmed instructions. The execution of the programmed instructions takes time, and therefore the switchover action must wait until the monitoring program completes its execution and issues the control signal to begin the switchover operation. The prior art hot-standby configurations are not sufficiently fast to permit high speed, high availability data processing in critical applications.